1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having a multi-layer wiring structure, and more particularly to a method of manufacturing a semiconductor device wherein a flattening step for an interlayer insulating film is improved.
2. Description of the Related Art
With reduction in size of a pattern of a semiconductor device, the surface configuration of the semiconductor device has been more complicated. On the other hand, with higher integration of circuit elements formed in a semiconductor device, the number of layers in a multi-layer wiring structure of the semiconductor device has increased more and more. In order to form a multi-layer structure, unevenness on the surface of the device needs to be flattened. Under the situation, a method of flattening an interlayer insulating film, etc. is very important. An example of such a flattening method is a CMP (Chemical Mechanical Polishing) method.
A conventional technique of flattening an insulating film with use of a CMP method will now be described with reference to FIG. 1.
A diffusion layer (not shown) of a transistor, etc. is formed on a semiconductor substrate 101. Then, a wiring layer 102 is formed on the semiconductor substrate 101 with a gate oxide film 105 interposed therebetween. An interlayer insulating film 103 is formed on the resultant structure. At this time, the surface of the interlayer insulating film 103 becomes uneven, as shown in FIG. 1, in accordance with the shape of the underlying wiring layer 102.
If the interlayer insulating film 103 is flattened by the CMP method, a dishing phenomenon occurs in the insulating film 103, as shown in FIG. 2.
According to another method, as shown in FIG. 3, a stopper film 104 having a lower polishing rate than the interlayer insulating film 103 is formed on the entire surface of the insulating film 103. Subsequently, the interlayer insulating film 103 is flattened by the CMP method. As a result, as shown in FIG. 4, a dishing phenomenon occurs in the insulating film 103. In the case where the stopper film 104 is provided, as the polishing step progresses to a certain horizontal point, the insulating film 103 and the stopper film 104 are polished at the same time. As a result, the polishing rate differs partly.
Specifically, the part of the insulating film 103 is polished more easily than the part of the stopper film 104. Owing to the load of the polishing table and the elasticity of the polishing pad, a recessed shape, as shown in FIG. 4, appears.
In order to prevent the dishing phenomenon, the interlayer insulating film 103 needs to be formed very thick. In this case, however, the polishing time and the manufacturing cost increase and the controllability is not good. Although there is a method of forming the stopper film 104 at only the recess of the interlayer insulating film, a lithography step is added (i.e. the cost increases). Besides, in order to prevent short-circuit between arranged wires, there is a method of forming a dummy pattern on the semiconductor substrate 101, thereby preventing provision of a space of a predetermined value between the wires. This, however, requires a precise pattern layout.
As has been described above, in the flattening method using the CMP method, a variance occurs in thickness of the polished interlayer insulating film owing to the unevenness of the pattern (chip pattern) underlying below the interlayer insulating film. In one method of preventing the variance, the thickness of the interlayer insulating film may be increased. In this case, however, the productivity decreases and the manufacturing cost increases.